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May 1997
ML4822* ZVS Average Current PFC Controller
GENERAL DESCRIPTION
The ML4822 is a PFC controller designed specifically for high power applications. The controller contains all of the functions necessary to implement an average current boost PFC converter, along with a Zero Voltage Switch (ZVS) controller to reduce diode recovery and MOSFET turn-on losses. The average current boost PFC circuit provides high power factor (>98%) and low Total Harmonic Distortion (THD). Built-in safety features include undervoltage lockout, overvoltage protection, peak current limiting, and input voltage brownout protection. The ZVS control section drives an external ZVS MOSFET which, combined with a diode and inductor, soft switches the boost regulator. This technique reduces diode reverse recovery and MOSFET switching losses to reduce EMI and maximize efficiency.
FEATURES
s
s s s s s s
Average current sensing, continuous boost, leading edge PFC for low total harmonic distortion and near unity power factor Built-in ZVS switch control with fast response for high efficiency at high power levels Average line voltage compensation with brownout control Current fed gain modulator improves noise immunity and provides universal input operation Overvoltage comparator eliminates output "runaway" due to load removal UVLO, current limit, and soft-start Precision 1% reference *This Part Is End Of Life As Of August 1, 2000
BLOCK DIAGRAM (Pin configuration shown for 14-pin package)
VEAO 1 8 GND 2 IEAO OVP VCC VCCZ 13.5V 2.7V 12
FB 14 2.5V IAC 4 VRMS 5 ISENSE 3 RTCT 6
- +
VEA R+ FB
+ -
+
GAIN MODULATOR R-
IEA
+ - -
I LIMIT -1V S Q
+ -
R PFC OUT 11
OSC VCCZ REF
S R
Q Q ZVS OUT 10
13
REF S R Q Q
ZV SENSE 7
+ - -
PWR GND 9
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ML4822
PIN CONFIGURATION
ML4822 14-Pin DIP (P14) ML4822 16-Pin SOIC (S16W)
VEAO IEAO ISENSE IAC VRMS RTCT ZV SENSE
1 2 3 4 5 6 7
14 13 12 11 10 9 8 TOP VIEW
FB REF VCC PFC OUT ZVS OUT PWR GND GND
VEAO IEAO ISENSE IAC VRMS RTCT ZV SENSE N/C
1 2 3 4 5 6 7 8 TOP VIEW
16 15 14 13 12 11 10 9
FB REF VCC PFC OUT ZVS OUT PWR GND GND N/C
PIN DESCRIPTION (Pin number in parentheses is for 16-pin package)
PIN NAME FUNCTION PIN NAME FUNCTION
1 (1) 2 (2) 3 (3) 4 (4) 5 (5) 6 (6) 7 (7)
VEAO IEAO ISENSE IAC VRMS RTCT ZV SENSE
Transconductance voltage error amplifier output. Transconductance current error amplifier output. Current sense input to the PFC current limit comparator. PFC gain modulator reference input. Input for RMS line voltage compensation. Connection for oscillator frequency setting components. Input to the high speed zero voltage crossing comparator.
8 (10) GND
Analog signal ground.
9 (11) PWR GND Return for the PFC and ZVS driver outputs. 10 (12) ZVS OUT ZVS MOSFET driver output. 11 (13) PFC OUT PFC MOSFET driver output. 12 (14) VCC 13 (15) REF 14 (16) FB Shunt-regulated supply voltage. Buffered output for the internal 7.5V reference. Transconductance voltage error amplifier input.
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ML4822
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Shunt Regulator Current (ICC ) ................................. 55mA Peak Driver Output Current ............................... 500mA Analog Inputs ................................................... -0.3 to 7V Junction Temperature ............................................. 150C Storage Temperature Range ..................... -65C to 150C Lead Temperature (Soldering, 10 sec) ..................... 150C Thermal Resistance (JA) Plastic DIP ....................................................... 80C/W Plastic SOIC ....................................................110C/W
OPERATING CONDITIONS
Temperature Range ML4822CX ................................................ 0C to 70C ML4822IX .............................................. -40C to 85C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, RT = 52.3k, CT = 470pF, TA = Operating Temperature Range (Note 1)
PARAMETER VOLTAGE ERROR AMPLIFIER Input Voltage Range Transconductance Feedback Reference Voltage Open Loop Gain PSRR Output Low Output High Source Current Sink Current CURRENT ERROR AMPLIFIER Input Voltage Range Transconductance Input Offset Voltage Open Loop Gain PSRR Output Low Output High Source Current Sink Current OVP COMPARATOR Threshold Voltage Hysteresis ISENSE COMPARATOR Threshold Voltage Delay to Output -0.8 -1.0 150 -1.15 300 V ns 2.6 80 2.7 120 2.8 150 V mV VIN = 0.5V, VOUT = 6V VIN = 0.5V, VOUT = 1.5V 6.0 -40 40 VCCZ - 3V < VCC < VCCZ - 0.5V 60 60 VNON-INV = VINV, IEAO = 3.75V -1.5 130 195 3 75 75 0.65 6.7 -80 80 1 2 310 15 V VIN = 0.5V, VOUT = 6V VIN = 0.5V, VOUT = 1.5V 6.0 -40 40 VCCZ - 3V < VCC < VCCZ - 0.5V VNON-INV = VINV, VEAO = 3.75V VEAO = VFB 0 50 2.4 60 60 70 2.5 75 75 0.65 6.7 -80 80 1 7 120 2.6 V V dB dB V V A mA CONDITIONS MIN TYP MAX UNITS
mV dB dB V V A A

3
ML4822
ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER ZV SENSE COMPARATOR Propagation Delay Threshold Voltage Input Capacitance GAIN MODULATOR Gain (Note 2) IIAC = 100mA, VVRMS = 0V, VFB = 0V IIAC = 50mA, VVRMS = 1.2V, VFB = 0V IIAC = 100A, VVRMS = 1.8V, VFB = 0V IIAC = 100A, VVRMS = 3.3V, VFB = 0V Bandwidth Output Voltage OSCILLATOR Initial Accuracy Voltage Stability Temperature Stability Total Variation Ramp Valley to Peak Voltage Dead Time CT Discharge Current REFERENCE Output Voltage Line Regulation Load Regulation Temperature Stability Total Variation Long Term Stability Short Circuit Current PFC COMPARATOR Minimum Duty Cycle Maximum Duty Cycle VIEAO > 6.7V VIEAO < 1.2V 90 95 0 % % Line, load, and temperature Tj = 125C, 1000 hours VCC < VCCZ - 0.5V, VREF = 0V -15 7.395 5 -40 TA = 25C, IREF = 1mA VCCZ - 3V < VCC < VCCZ - 0.5V 1mA < IREF, < 20mA 7.425 7.5 2 2 0.4 7.605 25 -100 7.575 10 15 V mV mV % V mV mA 100 4.5 Line, temperature 72 2.5 300 7.5 450 9.5 TA = 25C VCCZ - 3V < VCC < VCCZ - 0.5V 74 80 1 2 88 86 kHz % % kHz V ns mA IIAC = 250A VFB = 0V, VVRMS = 1.15V, IIAC = 250A 0.72 0.36 1.20 0.55 0.14 0.51 1.72 0.78 0.20 10 0.8 0.9 0.66 2.24 1.01 0.26 MHz V 100mV Overdrive 7.35 7.5 6 50 7.65 ns V pF CONDITIONS MIN TYP MAX UNITS
4
ML4822
ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER MOSFET DRIVER OUTPUTS Output Low Voltage IOUT = -20mA IOUT = -100mA IOUT = -10mA, VCC = 8V Output High Voltage IOUT = 20mA IOUT = 100mA Output Rise/Fall Time UNDERVOLTAGE LOCKOUT Threshold Voltage Hysteresis SUPPLY Shunt Voltage (VCCZ) Load Regulation Total Variation Start-up Current Operating Current
Note 1: Note 2:
CONDITIONS
MIN
TYP
MAX
UNITS
0.3 0.6 0.8 9.5 9 10.3 10.3 40
0.8 3.0 1.5
V V V V V ns
CL = 1000pF
VCCZ - 0.9 VCCZ - 0.6 VCCZ - 0.2 2.5 2.8 3.2
V V
ICC =25mA 25mA < ICC < 55mA Load and temperature VCC < 12.3V VCC = VCCZ - 0.5V
12.8
13.5 150
14.2 300 14.6
V mV V mA mA
12.4 0.7 22
1.1 28
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. Gain = K x 5.3 V; K = (IGAINMOD - IOFFSET) x IAC x (VEAO - 1.5)-1.
5
ML4822
FUNCTIONAL DESCRIPTION
Switching losses of wide input voltage range PFC boost converters increase dramatically as power levels increase above 200 watts. The use of zero-voltage switching (ZVS) techniques improves the efficiency of high power PFCs by significantly reducing the turn-on losses of the boost MOSFET. ZVS is accomplished by using a second, smaller MOSFET, together with a storage element (inductor) to convert the turn-on losses of the boost MOSFET into useful output power. The basic function of the ML4822 is to provide a power factor corrected, regulated DC bus voltage using continuous, average current-mode control. Like Micro Linear's family of PFC/PWM controllers, the ML4822 employs leading-edge pulse width modulation to reduce system noise and permit frequency synchronization to a trailing edge PWM stage for the highest possible DC bus voltage bandwidth. For minimization of switching losses, circuitry has been incorporated to control the switching of the ZVS FET. THEORY OF OPERATION Figure 1 shows a simplified schematic of the output and control sections of a high power PFC circuit. Figure 2 shows the relationship of various waveforms in the circuit. Q1 functions as the main switching FET and Q2 provides the ZVS action. During each cycle, Q2 turns on before Q1, diverting the current in L1 away from D1 into L2. The current in L2 increases linearly until at t2 it equals the current through L1. When these currents are equal, L1 ceases discharging current and is now charged through L2 and Q2. At time t 2, the drain voltage of Q1 begins to fall. The shape of the voltage waveform is sinusoidal due to the interaction of L2 and the combined parasitic capacitance of D1 and Q1 (or optional ZVS capacitor CZVS). At t3, the voltage across Q1 is sufficiently low that the controller turns Q2 off and Q1 on. Q1 then behaves as an ordinary PFC switch, storing energy in the boost inductor L1. The energy stored in L2 is completely discharged into the boost capacitor via D2 during the Q1 off-time and the value of L2 must be selected for discontinuous-mode operation. COMPONENT SELECTION Q1 Turn-Off Because the ML4822 uses leading edge modulation, the PFC MOSFET (Q1) is always turned off at the end of each oscillator ramp cycle. For proper operation, the internal ZVS flip-flop must be reset every cycle during the oscillator discharge time. This is done by automatically resetting the ZVS comparator a short time after the drain voltage of the main Q has reached zero (refer to Figure 1 sense circuit). This sense circuit terminates the ZVS on time by sensing the main Q drain voltage reaching zero. It is then reset by way of a resistor pull-up to VCC (R6). The advantage of this circuit is that the ZVS comparator is not reset at the main Q turn off which occurs at the end of the clock cycle. This avoids the potential for improper reset of the internal ZVS flip-flop. Another concern is the proper operation of the ZVS comparator during discontinuous mode operation (DCM), which will occur at the cusps of the rectified AC waveform and at light loads. Due to the nature of the voltage seen at the drain of the main boost Q during DCM operation, the ZVS comparator can be fooled into forcing the ZVS Q on for the entire period. By adding a circuit which limits the maximum on time of the ZVS Q, this problem can be avoided. Q3 in Figure 1 provides this function.
L1
D1
+ C1 VREF 13 VREF L2 CZVS(OPT) Q1 R3 22k R5 220 R6 22k 7 ZV SENSE C3 33pF C4 330pF 8 GND R2 Q3 PFC OUT 11 ZVS OUT 10 PWR GND 9 Q2 D2 R1 C2
ML4822
12 VCC
R4 51k
MAX ZVS ON TIME LIMIT
C5
Figure 1. Simplified PFC/ZVS Schematic.
6
ML4822
Q1 Turn-On The turn-on event consists of the time it takes for the current through L2 to ramp to the L1 current plus the resonant event of L2 and the ZVS capacitor. The total event should occur in a minimum of 350-450ns, but can be longer at the risk of increasing the total harmonic distortion. Setting these times equal should minimize conducted and radiated emissions. tQ1(OFF) = tIL2 + tRES = 400ns Where IL2 is equal to IL1. The value of L2 is calculated to remain in discontinuousmode: V x VRMS(MIN) x tIL2 L2 = BUS (2) 2 x POUT The resonant event occurs in 1/4 of a full sinusoidal cycle. For example, when a 1/4 cycle occurs in 200ns, the frequency is 1.25MHz. 1 1 fRES = = 4 x tRES (3) 2 L2 x CZVS Rearranging and solving for L2: L2 = 4 x tRES
2 2
D. VDS (Q2) C. ZVS GATE (Q2) A. SYSTEM CLOCK (INTERNAL)
(1)
B. RTCT
x CZVS
(4)
The resonant capacitor (CZVS) value is found by setting equations 2 and 4 equal to each other and solving for CZVS. 2 4 x tRES x 2 x POUT CZVS = 2 x VBUS x VRMS(MIN) x tIL2 (5)
E. PFC GATE (Q1)
APPLICATION
Figure 3 displays a typical application circuit for a 500W ZVS PFC supply. Full design details are covered in application note 33, ML4822 Power Factor Correction With Zero Voltage Resonant Switching.
F. VDS (Q1)
G. IL2
t1 t2
t3
Figure 2. Timing Diagrams
7
8
D1 B1 R12 453k 1% R13 402k 1% R23 402k 1% R15 16.2k 1% C6 0.47F 16V D5 D1N4747 R6 10k C2 470pF 1600V C1 330F 450V
+
F1 400VDC L1 420uH @ 10A n = 57 HFA15TB60 D2 D3 MUR460 HFA08TB60 R8 93.1k 1% R9 93.1k 1% R20 93.1k 1% R11 2.37k 1% C3 1000pF 50V 400VDC RTN C21 0.1F 200V D4 BYV26C Q2 IRF830 R1 3.3k 3W R10 102k 1% L2 8.5 @ 14A
LINE 8AMP 250VAC R22 453k 1% R14 100k 1% R3 10 D6 D1N4747 C4 0.1F 50V R4 10k Q1 IRFP460
ML4822
C14 0.47F 250VAC
250JB6L
NEUTRAL
R18 0.0732 5W 1% D13 1N5401 1 NC IN A 3 C12 2.2nF 50V C7 0.68F 50V R17 220k C13 100pF 50V C11 0.068F 50V 4 VS RTN IN B 2 D7 1N5401 TC4427 NC OUT A VS OUT B 8 7 6 5 C9 1F 50V R2 10
C10 1F 50V
D10 BYV26C R19 10k VEAO IEAO ISENSE IAC PFC OUT ZVS OUT PWR GND GND 10 9 8 VRMS RTCT ZV SENSE 11 VCC 12 REF 13 FB 2 3 4 5 6 7 1 14
Figure 3. ML4822 Scematic
ML4822
R21 39k 2W R5 39k 2W
R27 220
R16 8.25k 1%
R24 22k
C8 2.2F 50V
C5 1F 50V
R7 47 C15 1500F 25V C16 1F 50V
D11 BYM 12-50 L1 n = 2.5
R25 51k R26 22k
C18 33pF 50V Q3 2N7000
R29 10k C22 100pF
D9 PRLL5819 D8 PRLL5819 1N4148
C17 1F 50V
C19 330pF 50V
C20 2.2nF 50V
D12 BYM12-50
ML4822
PHYSICAL DIMENSIONS inches (millimeters)
Package: P14 14-Pin PDIP
0.740 - 0.760 (18.79 - 19.31) 14
PIN 1 ID
0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.25)
0.070 MIN (1.77 MIN) (4 PLACES)
1 0.050 - 0.065 (1.27 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN)
0.170 MAX (4.32 MAX)
0.125 MIN (3.18 MIN)
0.016 - 0.022 (0.40 - 0.56)
SEATING PLANE
0 - 15
0.008 - 0.012 (0.20 - 0.31)
11
ML4822
PHYSICAL DIMENSIONS inches (millimeters)
Package: S16W 16-Pin Wide SOIC
0.400 - 0.414 (10.16 - 10.52) 16
0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID
1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0 - 8
0.090 - 0.094 (2.28 - 2.39)
0.012 - 0.020 (0.30 - 0.51)
SEATING PLANE
0.005 - 0.013 (0.13 - 0.33)
0.022 - 0.042 (0.56 - 1.07)
0.009 - 0.013 (0.22 - 0.33)
ORDERING INFORMATION
PART NUMBER ML4822CP ML4822CS ML4822IP ML4822IS TEMPERATURE RANGE 0C to 70C 0C to 70C -40C to 85C -40C to 85C PACKAGE 14-Pin PDIP (P14) (EOL) 16-Pin Wide SOIC (S16W) (EOL) 14-Pin PDIP (P14) (EOL) 16-Pin Wide SOIC (S16W) (EOL)
(c) Micro Linear 1997 Micro Linear is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295
DS4822-01
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